The present invention relates to a semiconductor memory device; more particularly, to a semiconductor memory device performing a refresh operation.
A semiconductor memory device is an apparatus for storing a plurality of data and reading the stored data. The semiconductor memory device comprises a data storage area, a peripheral area and an I/O area. In the data storage area, there are a plurality of unit cells for storing data; and, in the peripheral area, there are circuits for inputting data into the plurality of unit cells or outputting data from the plurality of unit cells.
A dynamic random access memory (DRAM), generally used as a semiconductor memory device, includes a MOS transistor and a capacitor constituting a unit cell. In order for the DRAM to store more data within a closed size, it is required that the MOS transistor and the capacitor are fabricated smaller.
A semiconductor memory device such as a DRAM uses a capacitor as an element for storing data. Because the capacitor has characteristic of losing charges corresponding to the data as time passes away, the semiconductor memory device should regularly refresh the data stored in the capacitor. The semiconductor memory device supplies charges to the capacitor according to stored data before the charges stored in the capacitor decreases under a predetermined level, which is called a refresh operation.
The refresh operation includes an auto refresh operation and a self refresh operation. While accessing data, a semiconductor memory device receives a command relating to the auto refresh operation from an external device and performs the auto refresh operation. The self refresh operation is performed when the semiconductor memory device does not access data, for example, during a power down mode. The semiconductor memory device generates a periodic signal in response to an inputted command relating to the self refresh operation. The semiconductor memory device performs the self refresh operation according to the periodic signal.
A semiconductor memory device accesses data during an active operation and reading/writing operations. During the active operation, the semiconductor memory device receives a row address from an external device and selects a word line corresponding to the row address. Using bit line sense amplifiers, the semiconductor memory device senses and amplifies data stored in unit cells corresponding to the selected word line.
During the reading/writing operations, the semiconductor memory device outputs data corresponding to a column address among the amplified data or replaces the data with an input data from an external device. After the data are read or written, the data amplified by the bit line sense amplifiers are rewritten into the unit cells respectively. After the data are rewritten, a precharge operation is subsequently performed.
The refresh operation is processed like the active operation. However, the semiconductor memory device selects a word line coupled to cells to be refreshed not according to an external row address but to an address generated from an internal counter during the refresh operation. In addition, there is no reading/writing operation during the refresh operation. Data in unit cells corresponding to the selected word line are sensed and amplified by bit line sense amplifiers and restored into the unit cells respectively. The data are latched in the bit line sense amplifiers and restored into the corresponding unit cell after a predetermined time. The predetermined time for latching the data by the bit line sense amplifiers is determined according to a RAS timing of memory's specification.
The RAS timing means a time required when data in unit cells are sensed and amplified by bit line sense amplifiers and the amplified data are restored into the original unit cells during the refresh operation. Accordingly, it is important for the semiconductor memory device to maintain a RAS timing accurately.
A semiconductor memory device is generally manufactured with a RAS timing having a predetermined value according to an initial design requirement. However, after the semiconductor memory device is manufactured, the refresh operation of the semiconductor memory device may be not performed with the RAS timing according to the initial design requirement. That is, an actual RAS timing can be too long or short for the semiconductor memory device to perform the refresh operation. If the RAS timing is too long, a refresh operation time also increases and too much current is consumed. On the other hand, if the RAS timing is too short, the refresh operation is not performed sufficiently and, as a result, stored data can be lost.